1. Field of the Invention
The present invention relates to DMOS transistors and, more particularly, to a DMOS transistor with a slanted super junction drift structure.
2. Description of the Related Art
A metal-oxide-semiconductor (MOS) transistor is a well-known device that has heavily-doped source and drain semiconductor regions which are separated by a lightly-doped channel semiconductor region of the opposite conductive type. The MOS transistor also has an oxide layer that lies over the channel semiconductor region, and a metal gate that touches the oxide layer and lies over the channel semiconductor region. In addition to metal, the gate of a MOS transistor is also commonly formed with doped polysilicon.
A double-diffused MOS (DMOS) transistor is a power transistor that has a large lightly-doped drain semiconductor region, known as a drift region, which touches the channel semiconductor region and typically lies between the channel semiconductor region and the heavily-doped drain semiconductor region. DMOS transistors are commonly formed as lateral devices where the source and drain regions are horizontally spaced apart, and as vertical devices where the source and drain regions are vertically spaced apart.
In operation, vertical DMOS transistors typically provide better performance (e.g., a lower on-state drain-to-source resistance) than lateral DMOS transistors. Lateral DMOS transistors, however, are usually much easier to fabricate and, therefore, are less expensive to produce than vertical DMOS transistors.
FIG. 1 shows a cross-sectional diagram that illustrates a conventional vertical DMOS transistor 100 in accordance with the present invention. As shown in FIG. 1, vertical DMOS transistor 100 includes a semiconductor structure 110, such as a substrate or an epitaxial layer. Semiconductor structure 110, in turn, has an n+ drain region 112, an n− drain (drift) region 114 that touches and lies above n+ drain region 112, and a p− body region 116 that touches and lies above n− drift region 114.
Semiconductor structure 110 also includes an opening 122 that extends through p-body region 116 into n− drift region 114. Opening 122 has a bottom surface 124 and a side wall surface 125. In addition, semiconductor structure 110 includes n+ source regions 126A and 126B that touch p− body region 116. Depending on the vertical DMOS architecture that is utilized, the source regions 126A and 126B can be spaced apart or touch each other as a single region. As shown, n− drift region 114 and the n+ source regions 126A and 126B are vertically spaced apart and separated by channel regions 128A and 128B, respectively, of p− body region 116.
As further shown in FIG. 1, vertical DMOS transistor 100 also includes a gate oxide layer 136 that touches n− drift region 114 and p− body region 116 to line the bottom surface 124 and the side wall surface 125 of opening 122. In addition, vertical DMOS transistor 100 also includes a gate 142 that touches gate oxide layer 136. Gate 142, which is conductive, lies within opening 122 and fills the remainder of opening 122.
In operation, a first positive voltage is placed on n+ drain region 112 and a second positive voltage is placed on gate 142, while ground is placed on p− body region 116 and the n+ source regions 126A and 126B. In response to these bias conditions, the channel regions 128A and 128B of p− body region 116 invert, and electrons flow from the n+ source regions 126A and 126B to n+ drain region 112.
One important characteristic of a DMOS transistor is the breakdown voltage BVdss of the transistor, which is the drain-to-body voltage at which the junction breaks down and a current undesirably flows between the n-drift region and the p-body region. Since DMOS transistors are power transistors, there is a need to handle larger voltages and, thereby, a need to increase the breakdown voltage BVdss of the transistor.
Another important characteristic of a DMOS transistor is the on-state drain-to-source resistance rDS(ON). As just noted, DMOS transistors are power transistors and, as a result, can pass large currents when turned on. As a result, there is a need to reduce the on-state drain-to-source resistance rDS(ON) of the transistor.